FIGS. 5(A) and 5(B) show an example of prior art redundancy circuit devices related to the present invention, in which an inhibit system construction is shown in particular. In these figures, the memory cells (not shown) are arranged into a matrix pattern at intersection positions between a plurality of bit line pairs and a plurality of word line pairs. Further, the cells arranged in the word line direction are selected by a main word line 1 and subsidiary word lines 2 divided into N-units of sections SC1 to SCN in the word line direction, which is referred to as a double word line memory system.
Further, in case there exist a defective memory cell, the defective cell can be replaced with a non-defective spare cell; that is, the redundancy can be achieved. In this case, the spare cell is selected by using a spare main word line 3 and a spare subsidiary word line 4 for redundancy.
Further, an address signal for accessing the memory cell is applied to an address input circuit 12 through an address input terminal 11. On the basis of the address signal, the address input circuit 12 generates a row address RA and a column address CA. The generated row address RA is given to a row partial decoder 13 and the generated column address CA is given to a column partial decoder 19, respectively.
The row partial decoder 13 is connected to a redundancy program circuit 14. Therefore, when a spare cell is required to be selected for redundancy, the redundancy program circuit 14 generates one of spare select signals SPE1 to SPEK to select any one of K-units of spare cells and further a redundancy enable signal RDE indicative of the spare cell selection for redundancy.
The row partial decoder 13 decodes the row address RA and then gives the decoded row address RA to a main word line driver 15 via a NOR circuit 5. Here, since the redundancy enable signal RDE is inputted from the redundancy program circuit 14 to the NOR circuit 5, when the redundancy is not achieved, the NOR circuit 5 outputs a signal for selecting the main word line 1 to the main word line driver 15 on the basis of the signal given by the row partial decoder 13. As a result, the main word line driver 15 drives the main word line 1 on the basis of the signal given by the row partial decoder 13.
On the other hand, when the redundancy is achieved, the redundancy program circuit 15 outputs the redundancy enable signal RDE for restricting the output of the NOR circuit 5 and the spare select signals SPE1 to SPEK for selecting any one of the K-units of spare cells. The spare select signals SPE1 to SPEK are given to spare main word line drivers 17 via NOT circuits 6, respectively to drive any one of the K-units of the spare main word lines 3.
On the other hand, the column partial decoder 19 decodes the column address CA and then gives the decoded column address CA to a section decoder 110. The section decoder 110 generates section select signals SD1 to SDN to select any one of the N-units of the sections and supplies the generated section select signals to subsidiary word line drivers 16 and spare subsidiary word line drivers 18, respectively. As a result, when the redundancy is not generated, any of the subsidiary word lines 2 is selected; and when the redundancy is generated, any of the spare subsidiary word lines 4 is selected.
In the construction as described above, when the memory cells (not shown) are normal, the main word line 1 and the subsidiary word line 2 are selected on the basis of an address signal inputted through the address input terminal 11.
On the other hand, in case any of the memory cells is defective, and therefore when the redundancy is generated with respect to the row address selected by the row partial decoder 13, a spare cell is selected by the redundancy program circuit 14. Further, on the basis of the selected result, the spare main word line 3 and the spare subsidiary word line 4 are both selected.
FIG. 6 shows a more detailed construction of the redundancy program circuit 14 shown in FIGS. 5(A) and 5(B).
The spare select signals SPE1 to SPEK are outputted on the basis of the respective programmed results of N-units of program sections 26.
A program section 26 includes a plurality of defective address program circuits 25 in correspondence to the row partial signals applied by the row partial decoder 13.
In the defective address program circuit 25, 4 fuse circuits 24 are provided in correspondence to the row partial signals XiXj, Xi/Xj, /XiXj and /Xi/Xj, respectively.
In the fuse circuit 24, a fuse 23 formed of poly silicon is provided so as to be cut off by a laser, for instance when a defective cell exits and thereby a program for replacing the defective cell with the spare cell must be prepared. When the fuse 23 is cut off, any of transfer gates 21 arranged in the defective address program circuit 25 can be selectively turned on.
In the defective address program circuit 25, since any one of the 4 transfer gates 21 can be turned on by cutting-off the fuse in the fuse circuit 24, any of the row partial signals XiXj, Xi/Xj, /XiXj and /Xi/Xj is selected by the transfer gates 21 and then outputted from the defective address program circuit 25.
In the other program sections 26, the defective address program circuits 25 are provided respectively so as to correspond to the other row partial signals XkX1, respectively. Further, the outputs of the defective address program circuits 25 are given to a NAND circuit 7 to obtain a logical result, and then outputted as the spare select signal SPE1 to SPEK via a NOT circuit 8 and a NOT circuit 9, respectively.
Further, when the spare select signal SPE1 to SPEK is outputted from any one of the K-units of the program sections 26, the outputted spare select signal is detected by a NAND circuit 27 and outputted as the redundancy enable signal RDE.
In other words, where the replacement with the spare cells has been programmed by cutting off the fuses 23 of the fuse circuits 24 and further the row address selected by the row partial decoder 13 is defective, the defective address of the memory cell can be detected by the defective address program circuits 25. As a result, the spare select signals SPE1 to SPEK are outputted by the program sections 26 provided for each spare cell, and at the same time the redundancy enable signal RDE is outputted.
As a result of the operation as described above, the output of the NOR circuit 5 is inhibited; that is, the access to the main word line 1 and the subsidiary word line 2 are inhibited. Instead, the spare main word line 3 is selected by the spare select signals SPE1 to SPEK, and the spare subsidiary word line 4 belonging to the selected spare main word line 3 is selected in one of the sections SC1 to SCN selected by the section decoder 110.
That is, in case there exists a defective cell, the defective cell is previously programmed in the redundancy program circuit 14. Further, when a defective cell is selected by the row partial decoder 13, both the main word line 1 and the subsidiary word line 2 are switched to the spare main word line 3 and the spare subsidiary word line 4 together on the basis of the previously prepared program of the redundancy program circuit 14, so that the spare cell can be selected.
In the redundancy system as described above, when the programmed defective address is found, since the redundancy enable signal RDE is outputted not to select the defective address but to select the spare address, this system is referred to as inhibit system.
FIGS. 7(A) and 7(B) show the other example of the prior art redundancy circuit devices, which is referred to as isolation fuse system.
In FIGS. 7(A) and 7(B) the address input circuit 12 is connected to the row partial decoder 13, and the row partial decoder 13 outputs J-units of row decode addresses. Each row decode address is applied to the main word line driver 15 via a fuse 31. On the other hand, the redundancy program circuit 14 outputs K-units of spare select signals SPE1 to SPEK. Each spare select signal is applied to the spare main word line driver 17.
As a result, it is possible to select one of J-units of the main word lines 1 and the one of K-units of the spare main word lines 3. Further, in each of the main word lines 1, M-units of the subsidiary word lines 2 are arranged in correspondence to each of the sections SC1 to SCN. Further, in each of the spare main word lines 3, M-units of spare subsidiary word lines 4 are arranged in correspondence to each of the sections SC1 to SCN.
On the other hand, the address input circuit 12 is connected to the column partial decoder 19, and the column partial decoder 19 outputs the column address decode signal to the section decoder 110. The section decoder 110 outputs the section select signals SD11 to SC1M and SDN1 to SNDM to select the subsidiary word line 2 or the spare subsidiary word line 4 for each section SC1 to SCN, so that the subsidiary word line 2 or the spare subsidiary word line 4 can be selected separately for each section.
In the construction as described above, when there exists a defective address, the fuse 31 is cut off by a laser so that the defective address cannot be selected. Further, when the defective address is hit (i.e., found), one of the spare select signals SPE1 to SPEK outputted as a spare address programmed by the program section 26 is selected. In this case, although the address corresponding to the defective cell is accessed, since the fuse 31 is cut off, only the spare cells can be accessed.
In the above-mentioned isolation fuse system, since the number of the circuits controlled on the basis of the redundancy enable signal RDE is smaller as compared with the case of the inhibit system, it is regarded that the deterioration of the access time for redundancy is less.
In both the inhibit and isolation fuse systems, however, the defective cell is replaced with the spare cell for each main word line 1. In other words, in the case where the memory cells are divided into a plurality of sections as with the case of the double word line system, it is necessary to replace all of the subsidiary word lines connected to one main word line simultaneously with the spare cells.
On the other hand, in the case of the isolation fuse system as shown in FIGS. 7(A) and 7(B) since M-units of the subsidiary word lines 2 and the subsidiary word line drivers 16 are both connected to one main word line 1, when one main word line 1 and one section are selected, one of the M-units of spare main word lines 3 can be selected on the basis of the section select signals SD11 to SC1M and SDN1 to SDNM. The decode system as described above is referred to as modulation double word line system.
The modulation double word line system as described above is usually adopted when the addresses in one word line direction cannot be decided by one row decoder due to the problem related to the pattern area of the row partial decoder 13. In this redundancy system, however, when the defective cells are replaced with the spare cells for each main word line 1, it is necessary to replace M-units of the word line direction addresses at the same time.
As described above, in the prior art redundancy circuit device, when a defective cell is replaced with a spare cell in the double word line system memory cells, since the replacement is achieved for each main word line, a plurality of memory cells of the sections having no defective cell must be replaced simultaneously, so that the replacement is not effective.
On the other hand, in the case of the modulation double word line system memory cells, since a plurality of non-defective word line direction addresses are replaced simultaneously. Therefore, in the case of a 4 modulation double word line system, for instance, even if the spare cells for 4 addresses are prepared, since 4 spares must be replaced simultaneously, in practice only one address can be remedied, so the replacement efficiency is low.
Recently, with the advance of memory capacity, the replacement of defective cells with the spare cells has required more and more. In the prior art redundancy circuit device, however, in the case where a great number of spare cells cannot be prepared for reasons of chip area, there arises a problem in that the lower efficiency of the redundancy causes a reduction in the production yield of the memory chip.